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Silicon Labs /SiM3_NRND /SIM3L167_C /CLKCTRL_0 /APBCLKG1

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Interpret as APBCLKG1

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31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (DISABLED)MISC0CEN 0 (DISABLED)MISC1CEN

MISC0CEN=DISABLED, MISC1CEN=DISABLED

Description

APB Clock Gate 1

Fields

MISC0CEN

Miscellaneous 0 Clock Enable.

0 (DISABLED): Disable the APB clock to the VMON0, LDO0, EXTOSC0, LPOSC0, RTC0 and RSTSRC modules.

1 (ENABLED): Enable the APB clock to the VMON0, LDO0, EXTOSC0, LPOSC0, RTC0 and RSTSRC modules.
MISC1CEN

Miscellaneous 1 Clock Enable.

0 (DISABLED): Disable the APB clock to the Watchdog Timer (WDTIMER0) and DMA Crossbar (DMAXBAR0) modules.

1 (ENABLED): Enable the APB clock to the Watchdog Timer (WDTIMER0) and DMA Crossbar (DMAXBAR0) modules.

Links

()

Register Reference

https://github.com/cmsis-svd/cmsis-svd-data